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Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

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Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

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Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks

Parallel vs. Serial Inter-plane communication using TSVs

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

3.5-D Integration: A Case Study

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Parallel vs. Serial Inter-plane communication using TSVs

3.5-D Integration: A Case Study