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Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

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Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

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Characterization of Plasma-Induced Damage of Selectively Recessed GaN/InAlN/AlN/GaN Heterostructures Using SiCl4 and SF6

Metal-related gate sinking due to interfacial oxygen layer in Ir/InAlN high electron mobility transistors

Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

Asymmetrically strained all-silicon Tunnel FETs featuring 1V operation

Carbon-Based Field-Effect Transistors for Nanoelectronics

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

DRAM Based on Hysteresis in Impact Ionization Single-Transistor-Latch

Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters

Metal-related gate sinking due to interfacial oxygen layer in Ir/InAlN high electron mobility transistors

Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model

Characterization of Plasma-Induced Damage of Selectively Recessed GaN/InAlN/AlN/GaN Heterostructures Using SiCl4 and SF6

Asymmetrically strained all-silicon Tunnel FETs featuring 1V operation

Carbon-Based Field-Effect Transistors for Nanoelectronics

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

DRAM Based on Hysteresis in Impact Ionization Single-Transistor-Latch

Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters