Empirisme logique

Résumé

L'empirisme logique (parfois nommé positivisme logique, néo-positivisme, ou empirisme rationnel) est une école philosophique principalement illustrée par le Cercle de Vienne, fondée par un groupe réunissant des scientifiques et philosophes viennois dans les années 1920. Le Cercle de Vienne était avant tout un lieu de discussion entre scientifiques (Niels Bohr et Einstein y sont occasionnellement intervenus) et philosophes qui ne partageaient pas les mêmes convictions. Il se forme autour du philosophe Moritz Schlick, et on y trouve notamment les mathématiciens Hans Hahn et Karl Menger, le physicien Philipp Frank, le sociologue Otto Neurath, les philosophes Rudolf Carnap et Victor Kraft, ainsi que des étudiants en philosophie comme Friedrich Waismann et Herbert Feigl. À la même époque, à Berlin, des sympathisants se regroupent autour de Hans Reichenbach et de la Gesellschaft für Empirische Philosophie (Société pour la philosophie empirique). Fondée en 1928, celle-ci accueillit Carl Gust

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https://fr.wikipedia.org/wiki/Empirisme_logique

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Integrated Circuits and Logic Operations Based on Single-Layer MoS2

Andras Kis, Branimir Radisavljevic

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS2 represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS2. Our integrated circuits are capable of operating as inverters, converting logical “1” into logical “0”, with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS2 transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

2011

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Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on modifiable boundary conditions as defined and analyzed in our previous work. The logical state of a PMM is defined by its stability and logical operations are implemented by modifying the stability behavior of the mechanism. Our programmable logic device has two qualitatively different sets of inputs. The first set determines the logic function to be computed. The second set represents the logical inputs. The output is a single logical value, "true" if the mechanism changes state and "false" otherwise. In this way, we are able to mechanically implement a set of binary logical operations. This implementation is validated using an analytical model characterizing the qualitative stability behavior of the mechanism. This was further verified using finite element analysis and experimental demonstration.

AMER SOC MECHANICAL ENGINEERS2020

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PLP: Page Latch-free Shared-everything OLTP

Anastasia Ailamaki, Frederick Ryan Johnson, Ippokratis Pandis, Pinar Tözün

Scaling the performance of shared-everything on-line transaction processing to highly-parallel multicore hardware remains a great challenge for database system designers. Developments in OLTP technology remove locking and logging from being scalability bottlenecks on such systems, leaving page latching as the next potential problem. To tackle the page latching problem, we design a system around physiological partitioning (PLP). The PLP design applies logical-only partitioning, maintaining the desired properties of shared-everything designs, and introduces a multi-rooted B+Tree index structure (MRBTree) which allows us to partition the accesses at the physical page level. That is, logical partitioning, along with MRBTrees ensure that all accesses to a given index page come from a single thread and, hence, can be entirely latch-free. We extend the design to make heap page accesses thread-private as well. The elimination of page latching allows us to simplify key code paths in the system such as B+Tree operations leading to more efficient yet easier maintainable code. The profiling of a prototype PLP system shows that it acquires 85% and 68% fewer contentious critical sections per transaction than an optimized conventional design and one based on logical-only partitioning respectively. As a result the PLP prototype improves performance by up to 40% and 18% over the two systems on two multicore machines.

2011

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