Monocrystalline silicon | EPFL Graph Search

Monocrystalline silicon, more often called single-crystal silicon, in short mono c-Si or mono-Si, is the base material for silicon-based discrete components and integrated circuits used in virtually all modern electronic equipment. Mono-Si also serves as a photovoltaic, light-absorbing material in the manufacture of solar cells. It consists of silicon in which the crystal lattice of the entire solid is continuous, unbroken to its edges, and free of any grain boundaries (i.e. a single crystal). Mono-Si can be prepared as an intrinsic semiconductor that consists only of exceedingly pure silicon, or it can be doped by the addition of other elements such as boron or phosphorus to make p-type or n-type silicon. Due to its semiconducting properties, single-crystal silicon is perhaps the most important technological material of the last few decades—the "silicon era", because its availability at an affordable cost has been essential for the development of the electronic devices on which the

Additive Fabrication of Silicon Pillars on Monocrystalline Silicon by Direct Laser Melting

Marie Camille Laëtitia Le Dantec

Additive Manufacturing (AM) is an emerging part production technology that offers many ad-vantages such as high degree of customization, material savings and design of 3D highly complex structures. However, AM is a complex multiphysics process. Therefore, only a limited number of materials can already be commercially used to produce parts and a handful of others are being studied or developed for such process. Consequently, limited knowledge on this process is available, especially concerning materials that present thermomechanical challenges such as brittle materials. The present research focuses on additive fabrication of silicon pillars on a monocrystalline silicon wafer by Direct Laser Melting (DLM) with a pulsed 1064 nm laser beam. The simple geometry of pillars allowed for the first determining steps into process understanding. Several results were achieved through this PhD work. First, crack-free silicon pillars were successfully built onto monocrystalline silicon wafers. With the help of in-situ process monitoring and sample characterization, wafer substrate temperature and laser repetition rate were found to be the main influential parameters to obtain crack-free samples, as minimum substrate temperature of 730°C and a minimum repetition rate of 100 Hz were necessary to reach this goal (for a feed rate of 15 g/min and a pulse duration of 1 ms). The influence of secondary process parameters such as feed rate and energy per pulse were also discussed. A simple Finite Element Modeling (FEM) model validated by the experiments was used to explain crack propagation in the samples. Then, process monitoring of the DLM process was realized. High-speed camera image analysis re-vealed that vertical stage speed and powder feed rate should match to obtain a constant pillar building rate. As all pillars presented necking at their base, estimations of the thermal characteristics of the pillar during growth were carried out by FEM simulations. They were additionally used to explain the pillar final shape. Finally, the microstructure of the pillars built was characterized by the Electron Back-Scattering Dif-fraction (EBSD) technique. In the conditions presented in this work, the microstructure of the pillar was found to be in the columnar growth mode. The feed rate was identified as the most influential parameter on the microstructure, followed by the stage speed, the impurity content of the powder and the crystallographic orientation of the substrate. Epitaxial growth was achieved on more than 1 mm with a feed rate of 1.0 g/min, a stage speed of 0.1 mm/s, a powder with purity of 4N and a oriented wafer substrate. This work could be further continued by making improvements to the DLM setup, studying the influence of additional process parameters on the thermomechanical behavior and the microstructure control of the pillars, and/or using these results to realize more complicated shapes, either with this setup or by using a powder bed technique.

EPFL2018

Thermal management of components for high energy physics experiments and space applications

Timothée Robert Sophus Frei

High-energy physics (HEP) experiments and space missions share a common challenge: thermal management in harsh environments. The severe constraints in both fields make cooling of electronic components a major design concern. This thesis aims to develop high thermal conductivity, radiation hard devices for thermal management in HEP and space application with the help of micro-technologies.Continuous advances in micro-engineering have opened the door to the development of smaller and more efficient cooling devices capable of handling increasing power densities with minimum mass and volume penalties. In this respect, previous works have focused on the use of microchannels etched in single crystal silicon (ScSi) wafers to circulate a cooling fluid. However, whilst this technique represents the state-of-the-art for thermal management of silicon detectors, it poses several challenges, particularly those associated with the fluidic interconnections, compatibility with high operating pressures and coverage of large areas. A cooling scheme relying on two independent fluidic loops is proposed to overcome these limitations. The two cooling loops, referred to as the primary and the secondary cooling loops (i.e. PCL and SCL respectively), are connected through thermal and mechanical interfaces but do not share any fluidic interface. Both circuits work together to remove heat and control the temperature of multiple electronic components. The SCL transfers the heat generated at the source to the PCL, which transports it further away and dissipates it to the environment.The present thesis investigates the use of micro-oscillating heat pipes (uOHPs) to implement the secondary cooling loops. These devices offer great potential, particularly if embedded in silicon substrates. However, a better understanding of the mechanisms responsible for their self-actuated, two-phase flow is essential to produce high performance devices which meet the stringent requirements of particle detectors and spacecraft. Two types of dual-diameter uOHPs were microfabricated: the first version used a glass wafer to close trenches etched in a silicon substrate, while an all-silicon construction was adopted in the second type. The thermocompressed interface used to bond the two silicon wafers yielded excellent pressure resistance. The thermal performance of the of uOHPs was studied for different working fluids, charging ratios, orientations, and heat inputs, taking advantage of the transparent cover in the glass devices to monitor the two-phase flow for the different conditions. The results revealed that the performance of the proposed uOHPs was orientation-independent. Furthermore, under certain conditions the equivalent thermal conductivity of acetone-charged devices exceeded that of an equivalent copper strip.Finally, an innovative technique for charging and sealing the micro-cooling heat pipes was developed. It offers a low-volume, small-footprint solution to enclose working fluids in the devices. The proposed technique, which relies on a compressed Indium preform to seal the inlet charging port, yield very good leak-tightness results.

EPFL2021

Nanogap MEM resonators on SOI

Nicoleta-Diana Ciressan

Today's consumer electronics based on a large variety of time-keeping and frequency reference applications is based on quartz-crystal oscillators, because of their excellent performances in terms of quality factor, thermal and frequency stability. However, macroscopic size and CMOS incompatibility of quartz-crystal resonators draw a major limit on the miniaturization of wireless communication applications. For this reason, silicon microelectromechanical (MEM) resonators are considered promising candidates to replace quartz-oscillators in VLSI communication systems, due to their compactness, design flexibility and CMOS process compatibility. This work reports on the design, fabrication and characterization of MEM bulk lateral resonators with resonance frequencies in the order of tens of MHz. The need of stable, low cost and high yield processes for fabricating devices with extremely narrow (sub 100 nm) transduction gaps is a main research driver, together with the requirements of improved designs which include high quality factors and appropriate power handling. We are investigating two major designs: (1) longitudinal beam resonators and (2) novel fragmented-membrane resonators that respond to both high quality factor (Q) and low motional resistance (Rm) requirements. We propose several design optimizations for solving some of the issues which currently affect the MEM resonator performance, like the frequency stability and Q enhancement through energy loss minimization. An original fabrication process is presented, which enables the manufacturing of SOI-based, fully monocrystalline devices with 100 nm transduction gaps and aspect ratios as high as [60:1], without the need of advanced lithography techniques. We successfully validate the fabrication process on two different SOI substrates, with silicon film thicknesses of 1.5 µm and 6.25 µm. This thickness range combined to the doping level corresponds to partially depleted SOI, which can be a substrate of choice for the fabrication of future integrated hybrid MEMS-CMOS integrated circuits for communication applications. The fabricated structures are successfully characterized, demonstrating excellent resonator performance at room temperature. Q's as high as 235'000 and Rm's as low as 59 kΩ have been extracted in vacuum. Atmospheric pressure frequency response measurements of the fragmented membrane resonators show Q's of 3'600. This value is among the best reported to date, opening the possibility for atmospheric pressure applications such as mass-detection for gas sensing applications with detection done without a special package, just by direct exposure of the resonator to the environment. A novel study on temperature dependence (between 80 K and 320 K) of the fragmented membrane resonators is presented and discussed. Significant Q increase and Rm reduction are experimentally observed at cryogenic temperatures. The bulk mode resonators developed and discussed in this thesis can successfully be integrated in oscillator circuits, as we demonstrate by simulating a Pierce topology based on the calibrated equivalent circuit model of a 24.48 MHz fragmented membrane BLR. Our oscillator shows very good phase-noise performance of -142 dBc/Hz at 1 kHz offset from the carrier and the noise floor at -144 dBc/Hz, which nearly meets the GSM specifications.

EPFL2009