Test of VLSI Systems: ATPG and Fault Coverage

Related lectures (30)

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Explores defects, errors, and fault models in VLSI systems, emphasizing fault collapsing and dominance.

Explores Karnaugh maps, TTL gates, analog aspects of digital logic, and prime implicants.

Covers the generation of test vector patterns, fault modeling, structural vs. functional tests, and the implementation of time-frame expansion.

Discusses logic synthesis techniques for designing efficient digital circuits using minterms, maxterms, and new gates like XOR and XNOR.

Covers the Logical Effort method for optimizing logic delay and gate sizing impact.

Explores TTL gates, analog aspects, and various logic gates in digital circuits.

Covers linked and unlinked faults in VLSI systems, March test algorithms, critical paths, and path-delay fault testing.

Explores DFT techniques, scan design, JTAG boundary scan, and system test logic.

Introduces Logisim Evolution, focusing on basic components for digital circuit design.

Discusses logic synthesis techniques for designing efficient digital circuits from functional descriptions and truth tables.