Application-specific integrated circuit

An application-specific integrated circuit (ASIC ˈeɪsɪk) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec. Application-specific standard product chips are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series. ASIC chips are typically fabricated using metal–oxide–semiconductor (MOS) technology, as MOS integrated circuit chips. As feature sizes have shrunk and chip design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 logic gates to over 100 million. Modern ASICs often include entire microprocessors, memory blocks including ROM, RAM, EEPROM, flash memory and other large building blocks. Such an ASIC is often termed a SoC (system-on-chip). Designers of digital ASICs often

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consuming a total of 205 mu W DC power from 0.48 V and 1 V supplies. Of the total power consumption, 56% (115 mu W) is consumed by the digital logic, 16% (33 mu W) by the on-chip clock oscillator, and 28% (57 mu W) by the RF switch used as a backscatter modulator. The ASIC broadcasts up to 1000 BLE advertising packets per second at a data rate of 1 Mbps, yielding a backscatter modulator efficiency of 57 pJ/bit. The device was validated in both cabled and wireless (over-the-air) measurement setups, demonstrating compatibility with unmodified smartphones as well as commercially available BLE chips, such as the Nordic Semiconductor nRF51822. With the wireless test setup used in this work, and assuming a +10 dBm carrier source, the ASIC has a theoretical maximum read range of 4.9 m using a smartphone as the receiver. Building from previous work in BLE backscatter communication using FPGA-based prototypes, this work provides an important quantitative demonstration of the size and power savings that can be achieved in a BLE-compatible backscatter ASIC.

IEEE2022

Analog microelectronic emulation for dynamic power system computation

Ira Nagel

Power system dynamic simulators can be classified according to multiple criteria, including speed, precision, cost and modularity (topology, characteristics and model). Existing simulators are based on time-consuming numeric algorithms, which provide very precise results. But the evolution of the power grid constantly changes the requirements for simulators. In fact, power consumption is steadily increasing; therefore, the power system is always operating closer to its limits. Moreover, focus is put on decentralized and stochastic green energy sources, leading to a much more complex and less predictable power system. In order to guarantee security of supply under these conditions, real-time control and online security assessment are of the utmost importance. The main requirement for power system simulators in this context thus becomes the simulation time. The simulator has to be able to reproduce power system phenomena much faster than their real-time duration. An effective way to accelerate computation time of power system stability simulators is based on analog emulation of the power system grid. The idea is to avoid the heavy, time-consuming numerical matrix calculations of the grid by using an instantaneous analog Kirchhoff grid, with which computation becomes intrinsically parallel and the simulation time independent of the power system topology size. An overview of the power system computation history and the evolution of microelectronics highlights that the renaissance of dedicated analog computation is justified. Modern VLSI technologies can overcome the drawbacks which caused the disappearance of analog computation units in the 1960s. This work addresses therefore the development of a power system emulation approach from its theoretical principles to the behavioral design and the microelectronic implementation of a first demonstrator. The approach used in this research is called AC emulation approach and is based on a one-to-one mapping of components of the real power system (generator, load and transmission line) by emulating their behavior on a CMOS microelectronic integrated circuit (ASIC). The signals propagating on the emulated grid are the shrunk and downscaled current and voltage waves of the real power system. The uniqueness of this emulation approach is that frequency dependence of the signals is preserved. Therefore, the range of phenomena that can be emulated with an AC emulator depends only on the implemented models. Within the framework of this thesis, we restrict our developments to transient stability analysis, as our main focus is put on emulation speed. v We provide behavioral AC emulation models for the three main power system components. Thereby, special attention is paid to the generator model, which is shown to introduce a systematic error. This error is analyzed and reduced by model adaptation. Behavioral simulation results validate the developed models. Moreover, we suggest custom programmable analog building blocks for the implementation of the proposed behavioral models. During their design, application specific requirements, as well as imperfections, calibration, mismatch and process-variation aspects, are taken into account. In particular, the design of the tunable floating inductance used in all three AC emulation models is discussed in detail. In fact, major design challenges have to be addressed in order to achieve an inductance suitable for our application. Finally, a first AC emulation demonstrator is presented. A benchmark using a fixed two- machine topology has been implemented using a 0.35μm 3.3V CMOS technology. The characteristics of the emulated components (i.e. generators and transmission lines) are reprogrammable, allowing short circuits to be emulated at different distances from the generator. The emulated phenomena are shown to be 10′000 times faster than real time, therefore proving the high-speed capabilities of AC emulation.

EPFL2013

Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments

Giacomo Ripamonti

DC-DC converters based on Application Specific Integrated Circuits (ASICs) have been developed in this doctoral work for the High-Luminosity Large Hadron Collider (HL-LHC) experiments at CERN. They step down the voltage from a 2.5 V line and supply a load current up to 3 A. The main focus has been the miniaturization of the converters while maintaining high efficiency, together with the improvement of the dynamic performance and the minimization of the impact of substrate parasitic devices. These are challenges that industry and research are facing to power modern microprocessors, with the aim of minimizing the system volume, cost and power consumption, while guaranteeing good regulation performance. Miniaturization is a key requirement for application in the HL-LHC experiments, since any added material is detrimental for the physics performance. In addition, the converters must be tolerant to a high magnetic field (up to 4 T) and to ultra-high levels of radiation. Tolerance to the magnetic field is achieved by employing air-core inductors (which are the bulkiest components on the board), while radiation-hard ASICs have been designed in this work in a commercial 130 nm CMOS technology by extensively applying hardening by design techniques. Converters using two different architectures have been designed: a buck converter, which had been identified in a previous work as a good option to achieve high efficiency and low mass, and a Resonant Switched-Capacitor (ReSC) converter, which can further increase the power density while keeping high efficiency. A novel dual-edge pulse width modulator for the buck converter that has improved dynamic performance compared to conventional solutions has been designed and implemented. Its small-signal response has been modeled, and the model has been validated by measurements. In addition, this thesis proposes an integrated system that monitors in real-time the voltage stress experienced by the devices of the buck converter and adjusts its operation accordingly, in order to guarantee the required reliability, while maximizing the efficiency. The main building block of this system has been designed and has proved to be fully functional. A substrate-currents-aware characterization method that allows the evaluation of the impact of substrate parasitic devices on the circuit performance and reliability has been also devised, and it has been applied to select the best floor-plan for the buck converter. A novel control scheme that optimizes the efficiency of the ReSC converter for the whole load current range by adopting different operation modes has been proposed and implemented. This thesis reports the steady-state analysis of each mode and a small-signal model for one of them. The buck converter uses a 100 nH inductor, and the last prototype shows a peak efficiency of 88.4% for the 2.5 V-to-1.2 V conversion. It complies with the radiation specifications, and mass production will soon start. The designed prototype ReSC converter employs a 12 nH inductor, and its area occupancy and thickness are respectively 20% and 55% lower than the buck. Its efficiency is larger than that of the buck converter in a range of conversion ratios and load currents, reaching a peak efficiency of 91.4% for the 2.5 V-to-1.2 V conversion. Radiation tests have highlighted that the converter complies with Total Ionizing Dose specifications. By introducing a few improvements, a future prototype could be close to production readiness.

EPFL2020