Combinational and Sequential ATPG

Related lectures (15)

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Covers the Logical Effort method for optimizing logic delay and gate sizing impact.

Explores test vector generation, ATPG algorithms, fault coverage, and path sensitization in VLSI systems.

Explores defects, errors, and faults in VLSI systems, including fault models and testing challenges.

Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.

Explores test techniques for digital VLSI systems, covering fault modeling, test-pattern generation, and design for testability.

Explores defects, errors, and fault models in VLSI systems, emphasizing fault collapsing and dominance.

Explores logical effort, optimum sizing, and branch efforts in VLSI design.

Covers the generation of test vector patterns, fault modeling, structural vs. functional tests, and the implementation of time-frame expansion.

Explores technology scaling, Moore's Law impact, and future trends in VLSI design.

Explores sequential elements in VLSI design, including latches, flip-flops, setup time, and hold time.